1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device, and, more particularly, to a non-volatile semiconductor memory device capable of selectively erasing data in a "memory cell-by-memory cell" basis.
2. Description of the Related Art
Great attention has been paid to non-volatile semiconductor memories, such as a FRAM (Ferro-electric Random Access Memory), EPROM (Erasable and Programmable Read Only Memory) and EEPROM (Electrically Erasable and Programmable Read Only Memory). The EPROM and EEPROM have a plurality of memory cells each including a floating gate for storing charges and a control gate for detecting a change in the threshold voltage in accordance with the quantity of charges stored in the floating gate. Therefore, data is stored using these types of memory cells. The EEPROM can erase data of the entire array of memory cells. The EEPROM includes a flash EEPROM which has the memory cell array separated to a plurality of blocks and can thus selectively erase data block by block. The flash EEPROM has the following advantages:
(1) Non-volatile property for stored data,
(2) Low consumed power,
(3) Electrically rewritable (rewritable on board), and
(4) Low cost.
Therefore, this flash EEPROM is widely applicable as a memory for storing programs or data in electronic devices, such as a portable telephone and a portable information terminal. There are two types of flash EEPROMs at present: split gate type and a stacked gate type.
U.S. Pat. No. 5,202,850 discloses a split gate flash EEPROM. As shown in FIG. 1, a split gate memory cell 201 has an N type source S and N type drain D, both defined on a P type single crystalline silicon substrate 102, a floating gate FG provided on a channel CH between the source S and drain D via a first insulator film 103, and a control gate CG located on the floating gate FG via a second insulator film 104. A part of the control gate CG is arranged as a select gate 105 on the channel CH via the first insulator film 103.
As shown in FIG. 2, a memory cell array 222 of the flash EEPROM has a matrix of split gate memory cells 201, a plurality of word lines WLa to WLz each commonly connected to the control gates CG of an associated row of memory cells 201, a plurality of bit lines BLa to BLz each commonly connected to the drains D of an associated column of memory cells 201, and a common source line SL connected to the sources S of all the memory cells 201. The word lines WL-WLz are connected to a row decoder 223, and the bit lines BLa-BLz are connected to a column decoder 224.
In a word line erase mode of the flash EEPROM, as shown in FIG. 3, a voltage of a ground level (=0 V) is applied to all the bit lines BLa-BLz and the common source line SL. A voltage of +15 V is applied to a selected word line WLm and the voltage of the ground level is applied to the other, non-selected word lines WLa-WLl and WLn-WLz. As a result, the potentials of the control gates CG of the memory cells 201a and 201b which are connected to the selected word line WLm are raised to +15 V.
When the potential of the control gate CG is +15 V and that of the drain D is 0 V, a relatively high electric field is produced between the control gate CG and the floating gate FG because the electrostatic capacitance between the floating gate FG and the drain D is significantly greater than that between the control gate CG and the floating gate FG. Consequently, a Fowler-Nordheim (FN) tunnel current flows to the floating gate FG from the control gate CG so that electrons in the floating gate FG are drained into the control gate CG. Accordingly, data stored in the memory cells 201a and 201b are erased. That is, erasure is performed to all the memory cells 201 that are connected to a selected one of the word lines WL-WLz. If a plurality of word lines among the entire word lines WL-WLz are selected at a time, data can be erased from all the memory cells 201 connected to the selected word lines. This erasure is called block erasure.
In the above word line erase mode, data is erased from all the memory cells 201 that are connected to any selected word line or word lines WL-WLz. In other words, erasure is executed word line by word line. Unfortunately, such erasure operation cannot be carried out to erase data of a single memory cell 201. Data erasure from a single memory cell alone may be accomplished as follows.
First, data is erased from all the memory cells that are associated with a word line to which an arbitrary memory cell to be erased is connected. Then, the data present before erasure is rewritten in the memory cells other than the arbitrary memory cell. In this manner, an arbitrary memory cell may be erased.
Disadvantageously, the execution of erasing and rewriting operations on the memory cells located on the wordline having the arbitrary memory cell, reduces the durability of the memory cells which did not require erasure in the first place. In fact, the number of data rewritings that may be performed on memory cells of a flash EEPROM is limited. This is because electrons that are injected into, or drained from the floating gates FG during erasing and rewriting operations must pass through the first and second insulator films 103 and 104. As is well known in the art, passing electrons in erase mode deteriorates the second insulator film 104, and passing electrons in write mode deteriorates the first insulator film 103. The degradation of the insulator films 103 and 104 unfortunately causes erasure and writing failures that hinder efficient data storage.
Further, repeated data erasures on memory cells that require no erasure increases power consumption and reduce operational speeds of a flash EEPROM. The above-described scheme of erasing data from a single memory cell therefore complicates control operations by memory controllers, i.e., increases the circuit area, and increases the burden on the controller. Consequently, these disadvantages reduce critical operational speeds of flash EEPROMs.
Yasuo Sato et al have disclosed the scheme that enables one bit erasure from a stacked gate flash EEPROM using one-transistor type memory cells (Singaku Technical Report, SDM93-23 CD93-25 (1993-05), pp. 9-14). The method in this paper performs data writing by using the FN tunnel current which flows to the floating gate from the drain. In the word line erasure (which is called "sector erasure" in this paper), the FN tunnel current which flows to the entire channel from the floating gate is used. In the one-bit erasure, the injecting of hot electrons into the floating gate from the channel are utilized.
This method however involves different erasing schemes for the word line erasure and the bit erasure, which complicates the whole circuit of the flash EEPROM. Furthermore, the stacked gate memory cells have a low efficiency in injecting hot electrons to the floating gate from the channel. This reduces the number of memory cells that may be simultaneously erased in a one-bit erase mode. When the FN tunnel current which flows to the floating gate from the drain is used in the write mode, a DINOR type or AND type memory cell structure should be employed to prevent disturbance. That is, a simple NOR type memory cell structure cannot be used.